#SOLVNET SYNOPSYS VERIFICATION#
Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. (NASDAQ: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. StarRC Custom is in limited customer availability now, with general customer availability planned in December 2009. The tools incorporate technologies such as hierarchical extraction, feature-scale chemical-mechanical polishing (CMP) effects modeling and variation-aware extraction to enable designers to achieve signoff accuracy while meeting their stringent tapeout schedules. The next-generation StarRC and StarRC Ultra solutions offer versatile solutions for full-chip, gate-level and transistor-level designs as well as technologies to support advanced analysis capabilities. StarRC Custom provides the foundation of an expanded Synopsys extraction tools suite, which includes StarRC and StarRC Ultra. Star-RCXT is already in use by more than 40 leading semiconductor companies at 45-nm and trusted on more than 140 tapeouts at 16 foundries. StarRC Custom solution is built on the Star-RCXT gold standard technology and environment, enabling custom IC designers to get the instant benefit of Star-RCXT's broadest qualification in the industry for 65-nm and 45-nm process nodes. To address this challenge, Synopsys took a unique approach with StarRC Custom by focusing not only on extraction runtime and accuracy, but also on optimizing the extraction data to improve overall transistor-level simulation throughput." "Increasing transistor count combined with the modeling of more complex parasitic effects is resulting in transistor-level simulation runtimes doubling and quadrupling. "The widespread use of custom circuits in today's complex system-on-chip (SoC) designs is creating a severe simulation and signoff bottleneck," said Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys. Additionally, StarRC Custom provides seamless integration with Synopsys' Galaxy Custom Designer™ implementation solution to improve designer productivity.
#SOLVNET SYNOPSYS SIMULATOR#
This comprehensive offering includes optimized links with Synopsys' technology-leading CustomSim™ circuit simulator which can boost simulation runtime by up to 10X while preserving signoff accuracy. By combining the gold standard Star-RCXT™ extraction technologies and the Raphael™ NXT 3D fast field solver into a single, unified extraction solution, the StarRC Custom solution offers high performance runtime with tuned accuracy to meet the analysis demands of high-sensitivity custom circuits.
#SOLVNET SYNOPSYS SOFTWARE#
(NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced its new StarRC™ Custom parasitic extraction solution for analog mixed-signal (AMS) and custom digital IC design. 21 / PRNewswire-FirstCall/ - Synopsys, Inc.